The invention relates generally to overvoltage and combined undervoltage protection circuits for protecting other circuits from higher and lower than desired voltage levels, and more particularly to voltage scaling circuits for protecting an input to a protected circuit.
With the continued demand for higher speed and lower power consumption integrated circuits a need exists for simple, low cost and reliable over voltage and undervoltage protection circuits. For example, CMOS based video graphics chips with 128 input/output ports (I/O) ports are required to operate at clock speeds in excess of 250 MHz. Such devices may use a 1.8 V power supply for much of its logic to reduce power consumption. One way to increase the operating speed of such devices is to decrease the gate oxide thickness and gate length of core circuitry transistors. However, a decrease in the gate oxide thickness and gate length of MOS devices can reduce the gate-source (gate-drain) operating voltage to lower levels. For example, where an integrated circuit contains digital circuitry that operates from a 1.8 V source and is fabricated using silicon dioxide gate thickness of 30 xc3x85, a resulting maximum operating voltage may be approximately two volts. Such IC""s must often connect with more conventional digital devices that operate at or 3.3 V. A problem arises when the core logic circuitry (operating, for example, at 1.8 V) receives 3.3 V digital input signals from peripheral devices on input pins. Such standard 3.3 V input signals can cause gate oxide damage if suitable voltage protection is not incorporated.
FIG. 1 shows a known over voltage protection arrangement that attempts to overcome the overvoltage problem. As seen, a resistor R is placed in the input path from an input pin P to the input I of a MOS based core logic stage, such as an input/output port on a CPU or other processing unit. A clamping diode D is placed across the input I of the core logic stage and is connected to a 2.5 V supply voltage used by the core logic to clamp over voltages coming from pin P. In operation, resistor R restricts current flow to the core logic circuit and a voltage drop occurs across the resistor. When an input voltage is high enough to cause the diode D to conduct, the diode clamps the input voltage to a fixed level (2.5 V+diode junction voltage drop). Several problems arise with such a configuration. If the core logic is fabricated with gate widths of 50 xc3x85, an input voltage of only 2.8 V is required to damage the core logic stage. With the diode drop of approximately 0.7 volts, a 3.5 V input voltage is a maximum input voltage to the core logic stage. However, with this 3.5 V level of damage voltage over temperature and time, circuit reliability may be compromised. This problem is more prevalent as the core logic supply voltage is reduced to 1.8V and the gate thickness is based on 0.18 um technology wherein the gate thickness is on the order of 30 xc3x85 or smaller gate thicknesses. Also, the clamp diode D allows additional current to flow through the substrate which can cause latch-up of core logic circuitry.
Another problem is the use of resistor R. Such resistive elements take up large areas on integrated circuits and dissipate large amounts of power, hence heat, when an input voltage such as 5 volts is placed on pin P. In addition, a large time delay can occur due to the resistor R and the parasitic capacitance of the gate junction of the core logic circuit. This time delay reduces the speed of operation of the system.
In addition, receivers may also experience undervoltage conditions, such as negative voltage undershooting due to different ground potentials between the peripheral circuitry and the receiver circuitry. With higher speed circuits, such as those using 0.18 micrometer MOS gate thicknesses, and having a 1.8 V supply voltage, such circuits may have to receive higher input voltages such as 3.3 V from peripheral circuits. An undesirable undervoltage condition, such as a xe2x88x920.4 V input signal may be experienced. As such, for a 1.8 V based receiver, the input on a node may experience a total potential of 1.8 V plus xe2x88x920.8 V resulting in a 2.6 V potential across a gate to drain or gate to source of a receiver transistor. This potential is typically higher than the normal operating voltage (2 V) and can damage the receiver MOS devices. Accordingly, it would be desirable to control an input voltage to a receiver such that undervoltage conditions and overvoltage conditions do not damage the receiver circuitry or the core logic circuitry or other circuit that has to be protected.
Moreover, there are different voltage supplies that are being used to power CMOS chip cores and I/O pads as well as different voltage level of input signals that are received or operated by the I/O pads. For example, with 0.18 micrometer technology, the core voltage may be 1.8 V based supply and I/O pad circuitry may be 2.5 V or 3.3 V. As such, the voltage level of the input signals to the I/O pads may be 2.5 V or 3.3 V. If it is desired to make a single gate oxide core logic and I/O pad logic, greater chips speeds and power reduction can occur. However, the 2.5 V or 3.3 V input signals could damage such transistors. In addition, as mentioned above, input signals can have an undershoot of 0.4 V or more.
Consequently there exists a need for a protection circuit that reduces power consumption, improves the speed of operation of a system in a simple and reliable manner. It would desirable if the protection circuit provided voltage scaling in a cost effective manner and also provided undervoltage protection (e.g., protection against negative input voltages).